1. The delta delay in VHDL is greater than zero, but less than any specified delay (the specified delay includes the inertia delay specified by after and the transmission delay specified by transport). Therefore, at a certain simulation time t, turning on a limited number of simulation cycles (ie, a delta delay) does not advance the simulation time, that is, no matter how many delta delays, it is considered to be at time t. Why can you think so, please see 2.
2. In specific hardware, processes occur in parallel, that is, data is always flowing into each module, and there is no first come and go between modules. Therefore, at one time t, multiple events will occur at the same time. However, the simulation software is implemented on a PC using a serial mechanism such as C language, so it is necessary to simulate parallel events as accurately as possible under the serial mechanism. What to do, there is a model of delta delay. In a simulation cycle (ie, a delta delay), the simulator processes each event serially, but we consider this simulation cycle as a whole to think that these events are macroscopically parallel. Since it is parallel, it is taken for granted that it is still at t.
3. A process starts a simulation cycle as long as an event occurs in its sensitive table at time t. In a simulation cycle, multiple processes can be activated at the same time, depending on whether there is an event in the sensitive table. But for a process, no matter how long it is, as long as there is no specific time delay such as after, it is considered to take a delta delay to complete, that is to say its result is updated after delta (can be understood as I figure it out immediately, but I will update it after the delta.) If its output is updated after the delta and another process is triggered, then another simulation cycle is opened and the delta is executed. It can be seen from 1 that no matter how many deltas are opened, it is considered to occur in parallel at time t. Note, however, that once there is an after process, the new value is considered to be updated at the specified time, regardless of delta.
4. for example.
(i) The following two lines are in an architecture:
Z <= X+Y;--(1)
A <= Z+B;--(2)
These two sentences can be seen as two processes. The current time is t1. At this time, X changes. Ok, activate (1), open a simulation cycle, and immediately calculate Z=X+Y, but wait until the delta delay to update the value of Z. Since the value of Z changes and activates (2), well, open another simulation cycle, calculate A=Z+B, and wait for the value of A after delta to update. Therefore, no matter who (1)(2) writes first, it is such a process, which takes a total of 2delta (still belonging to TI time).
(ii) Above we assume that B does not change when X changes. If B changes when X changes, then a simulation cycle is opened. In this cycle, (1) and (2) are simultaneously activated, and the values ​​of Z and A are calculated simultaneously (of course, the implementation of the simulator is sequential, but in delta Inside thinks parallel), after waiting for delta, Z and A are updated at the same time, but it must be noted that the A value at this time is calculated using the value before Z update. After that, the change of Z is activated again (2). At this time, the calculated A is the updated Z, but to wait for the delta, the A value is updated to the final result. Compared with (i), the results are the same and the time is the same, both are 2delta.
(iii) If (1) is changed to Z <= X+Y after 2ns, (2) is unchanged, then after X changes at time t1, it is considered that the Z value is updated at t1+2ns, regardless of the delta delay. After that, the delta delay A value is updated. So the total cost becomes delta+2ns.
(iv) If (1)(2) is in a process, then the situation is this. Since only one simulation cycle is opened in a process, (1)(2) is always done in one delta, so no matter who (1)(2) writes first, the final A value is calculated using the old value of Z. , there will be wrong results. This must be noted. This is also why assigning a signal multiple times in a process will only result in the last assignment. Because each assignment is updated after the end of the delta time.
5. To sum up, it is understood that the internal and after statements in a process can be understood as no longer opening the simulation cycle.
6. Let's take a closer look, why should the signal assignment wait for the delta delay? 2 said that it is due to the use of serial mechanisms to deal with parallel problems. In addition to this, it is also determined by the use and characteristics of the signal itself. The signal is mainly used for inter-process communication, and the signal needs to be driven. If an A process needs to read the value of signal Z and the B process writes the value of signal Z again, there will be a conflict in the simulation. By introducing a delta delay, the read and write staggered a delta time, solving the problem of simultaneous reading and writing of signals between processes.
7. Off-topic, explain the difference between inertia delay and transmission delay. The inertia delay is to make the output get the correct value and how long the input needs to be kept. such as
Z <= X after 2ns, indicating that X needs to remain at least 2ns, Z will get the value of X, otherwise the value of X may be eaten. The corresponding physical condition is to leave enough time for the capacitor to charge and discharge. Too short a pulse may be eaten. The problem of the transmission delay is that it does not eat or eat, that is, how long after the input is completely reproduced, no matter how short the pulse. such as:
Z<= transport X after 2ns means that the value of X is completely reproduced at the Z end after 2 ns. The corresponding physical condition is the transmission line.
Add to:
1. Adding a little thought, the delta delay model is useful when opening several simulation cycles at a time, such as a process that fires another process, etc., which really helps the transmission of signals between processes, at least in terms of analysis. The old values ​​are used in one delta, and the newly opened delta uses the updated value calculated by the previous delta. That's all.
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