1, description of the completeness of sensitive variables
In Verilog, when using the always block to design a combinational logic circuit, all signals participating in the assignment at the right end of the assignment expression must be listed in always @ (sensitive level list), and the expression of the if statement in always must be at a sensitive level. Listed in the list. If a signal not listed in the sensitive level list is referenced at the right end of the assignment expression, a transparent latch will be implicitly generated for the unlisted signal during synthesis. This is because the change of the signal does not immediately cause the change of the assigned value, but must wait until one of the signals in the sensitive level list changes, its function is expressed, that is, there is a transparent lock, the signal is The change is temporarily stored, and when a certain signal in the sensitive level list changes, the pure combination logic circuit cannot do this. The synthesizer will issue a warning.
Example1:
Input a,b,c;
Reg e,d;
Always @(a or b or c)
Begin
e=d&a&b; /*d is not in the list of sensitive levels, e does not change immediately when d changes until a change in a, b, c */
d=e |c;
End
Example2:
Input a,b,c;
Reg e,d;
Always @(a or b or c or d)
Begin
e=d&a&b; /*d In the list of sensitive levels, e changes immediately when d changes*/
d=e |c;
End
2, the description of the completeness of the condition If the conditional description of the if statement and the case statement is incomplete, it will also cause unnecessary latches.
Example1:
If (a==1'b1) q=1'b1;//If a==1'b0,q=? q will keep the original value and generate a latch!
Example2:
If (a==1'b1) q=1'b1;
Else q=1'b0; / / q has a clear value. No latches will be generated!
Example3:
Reg[1:0] a,q;
....
Case (a)
2'b00 : q=2'b00;
2'b01 : q=2'b11; / / If a == 2'b10 or a == 2'b11, q = ? q will keep the original value unchanged, the latch!
Endcase
Example4:
Reg[1:0] a,q;
....
Case (a)
2'b00 : q=2'b00;
2'b01 : q=2'b11;
Default: q=2'b00; //q has an explicit value. No latches will be generated!
Endcase
Description of the port in Verilog
1, the bit width of the port is best defined in the I / O description, not in the data type definition;
Example1:
Module test(addr,read,write,datain,dataout)
Input[7:0] datain;
Input[15:0] addr;
Input read, write;
Output[7:0] dataout; //To define the bit width of the port like this!
Wire addr,read,write,datain;
Reg dataout;
Example2:
Module test(addr,read,write,datain,dataout)
Input datain, addr, read, write;
Output dataout;
Wire[15:0] addr;
Wire[7:0] datain;
Wire read,write;
Reg[7:0] dataout; // Do not define the bit width of the port like this! !
2, the relationship between port I / O and data types:
The data type of the port's I/O port
Module internal module external
Input wire wire or reg
Output wire or reg wire
Inout wire wire
3, the left end of the assign statement must be wire; directly with "=" to assign a variable to the left variable must be reg!
Example:
Assign a=b; //a must be defined as wire! !
********
Begin
a=b; //a must be defined as reg!
End
Differences between STD_LOGIC_VECTOR and INTEGER in VHDL For example, A is an INTEGER type with a range from 0 to 255; B is an STD_LOGIC_VECTOR, defined as 8 bits. A tired to add 255
Time,
Adding 1 will keep 255 unchanged, and will not automatically reverse to 0 unless it is 0. When B is added to 255, adding 1 will automatically reverse to 0. So pay special attention when using it!
Take the trigger as an example to illustrate the normative description
1, no set/cleared timing logic
Always @( posedge CLK)
Begin
Q<=D;
End
2, there is asynchronous set/clear timing logic asynchronous set/clear is clock-independent, when the asynchronous set/clear signal comes, the output of the flip-flop is immediately set to 1 or 0, do not need to wait The clock edge is asserted/cleared. Therefore, the set/clear signal must be included in the event control expression of the always block.
Always @( posedge CLK or negedge RESET)
Begin
If (!RESET)
Q=0;
Else
Q<=D;
End
3. Timing logic with synchronous set/clear. Synchronous set/clear means that the output of the flip-flop can be converted to 1 or 0 only if it is set/cleared at the active transition time of the clock. Therefore, do not include the set/clear signal in the event control expression of the always block. However, the level of the set/clear signal must first be checked in the always block.
Always @( posedge CLK )
Begin
If (!RESET)
Q=0;
Else
Q<=D;
End
The coding of behavioral design and structural design is the most important step in the entire chip design project.
It has a significant impact on logic synthesis and routing results, timing measurements, verification capabilities, test capabilities, and even product support. Considering the difference between the simulator and the real logic circuit, in order to effectively perform the simulation test:
1. Avoid using internally generated clocks The internally generated clock is called the gated clock. If the external input clock and the gate clock are driven at the same time,
Inevitably, the pace of the two is inconsistent, causing logic confusion. Moreover, the gate clock will increase the difficulty and time of the test.
2. Absolutely avoid using internally generated asynchronous set/clear signals Internally generated set/clear signals can cause test problems. Some output signals are asserted or cleared and cannot be tested properly.
3. Avoid using latches Latches can cause test problems. For test vector auto generation (ATPG),
In order for the scan to proceed, the latch needs to be placed in a transparent mode.
In turn, the test latch needs to construct a specific vector, which can be quite general.
4. The timing process must have a clear reset value. The flip-flop has a reset terminal. During the manufacturing test, ATPG, and analog initialization, the entire circuit can be quickly reset.
5, to avoid tri-state / bi-directional in the module Internal tri-state signal is difficult to handle in the manufacturing test and logic synthesis process.
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