In the metallurgical industry, the transmission of most of the control information is basically based on the bus. Real-time monitoring of each production and processing link can be realized through the bus, so the bus technology is ubiquitous, and the VME computer supports multiple CPU, 64-bit addressing and data transmission capability, IEC 297 ohm card standard, reliable and stable mechanical performance, and reliable connectors, hot plugging, multi-vendor support and other advantages have been widely used. Here is a practical example of using a dual-port RAM to implement inverter and VME communication.
1 overall structure
As shown, the entire communication consists of three parts: DSP, VME dual-port RAM.
1.1 DSP part
This part is the core of the entire motor control system. DSP is mainly used to generate PWM pulses for controlling motors. The chip used in this project is Texas Instruments' TMS320LF2407A chip. It has two event managers inside, which can generate up to 12 pulse signals. It integrates high-performance 10-bit ADC. SCI, SPI, CAN and other modules, truly achieve single-chip control, stable performance and powerful functions.
1.2 VME bus
VME bus, Motorola's 32-bit industrial open standard bus introduced in 1981, mainly used in industrial control field, to achieve high-speed data acquisition, real-time communication between devices on the bus. The plug-in board of VME bus generally has two sizes, one is 3U height with one bus interface J1, the other is 6U height with 2 bus interfaces J1, J2. Generally, the interface of each VME bus plug-in board J1 and J2 have 96 pins. Each interface is 3 rows. It is arranged in A, B and C. Each row is 32 pins. J1 is generally used to connect directly to the VME bus. The middle column of J2 is used to expand the address bus or data. The bus, the other two columns are user-definable and I/O, disk drives and other peripherals. 1.3 Dual Port RAM Dual Port RAM has two sets of completely independent data lines, address lines, and read/write control lines, allowing two CPUs to simultaneously access the same unit of dual port memory; with two completely independent interrupt logics. Realize the handshake control signal between the two CPUs; have two sets of independent "busy" logic to ensure the correctness of read/write operations of the same CPU by the two CPUs at the same time; strong compatibility, read/write timing and common single port The memory is exactly the same, and the access speed fully meets the requirements of various CPUs. These features make dual-port RAM capable of high-speed, real-time communication applications. The dual port RAM has two sets of independent memory circuits, which are connected to each other by a control arbitration circuit. Take IDT7024 as an example, the chip is 4K*16 static memory, the typical power consumption is 750mW, and the maximum access time is 15/17/20/25/35/55ns. It can be coordinated by interrupt, busy logic and semaphore. Both sides of the information exchange.
2 hardware components
2.1 DSP part
Using the TMS320LF2407A chip, in order to connect to the dual-port RAM, the 16-bit data line and the 12-bit address line of the DSP should be taken out. In addition, there are control signal lines: DS, R/W.2.2 VME bus. The standard 6U chassis of VMIC is used here. , including J1, J2 two bus interfaces, only use J1 for communication. 2.3 Dual Port RAM Dual Port RAM has two sets of independent address and data lines, which are connected to the address and data line of DSP and VME bus respectively, and connect the control signal lines of J1 and DSP to the GAL. RAM is logically controlled, as shown in the following figure: 3 Communication flow Here we use VME as the master device and DSP as the slave device. The DSP read and write operations are controlled by VME. It should be noted that the same address cannot be written at the same time or read while reading to prevent the generation of data for writing and reading errors. The following are the flow charts for reading and writing communication:
If the VME "reads" data from the dual-port RAM, it is first necessary to determine whether the area in which the data is being read is being "written" by the DSP side, and can be judged by the "semaphore flag bit" to judge that the DSP does not operate the area. VME can read data from this area.
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