Voltage regulator modules (VRMs) that power the latest computer central processing units (CPUs) have traditionally used multiphase interleaved buck converters. These VRMs are designed to meet the strict regulation and transient requirements of high-performance CPUs like the Pentium 4 and Athlon. Interleaved buck converters are particularly well-suited for low-voltage, high-current applications because they significantly reduce the RMS current in both the input and output capacitors compared to standard buck converters. This results in smaller capacitor banks and improved efficiency. By interleaving two forward converters, designers can also achieve similar benefits as interleaving two buck converters. In high-current applications such as intermediate bus or commercial power supplies, using an interleaved forward converter can offer advantages over a standard forward topology.
The traditional forward converter has an input current that is interrupted and must be filtered through the input capacitor (Cin), resulting in higher RMS input current (Icin). The output filter inductor (L1) is sized to allow a ripple current (ΔIL1) of approximately 25% to 30% of the output current (Iout) to meet the output ripple voltage requirement (Vripple). The size of the output capacitor (Cout) is determined based on its ability to suppress the inductor ripple current. The following equations can be used to estimate the maximum equivalent series resistance (ESR) and minimum output capacitance (Cout). Typically, ESR is the main constraint, requiring higher capacitance to suppress ripple current effectively.
Interleaved dual forward converters operate with two forward converters phase-shifted by 180 degrees. This configuration reduces both the input capacitor RMS current and the output capacitor ripple current. Each converter’s input current is intermittent, but when interleaved, the total input current becomes more continuous, resembling DC. As a result, the input capacitor only needs to filter the AC portion of the current, allowing it to be much smaller. The output current is the sum of the two inductor currents minus the capacitor current. Because the inductors are interleaved at 180 degrees, their ripple currents cancel each other, leading to a smoother output and reducing the amount of ripple the output capacitor must handle. This allows for a higher ESR in the output capacitor without compromising performance.
In theory, the inductor ripple current cancellation feature could allow for smaller inductors. However, in high-current applications, inductors are often kept the same size to minimize total losses. The optimal capacitor ripple current reduction occurs at a 50% duty cycle. At this point, the input and output capacitor RMS currents are minimized. When the duty cycle is less than 50%, the input current becomes less continuous, increasing the RMS current in the input capacitor. Similarly, the output inductor ripple current becomes asymmetrical, reducing the effectiveness of ripple cancellation. This increases the ripple current that the output capacitor must handle.
The equations provided show how the input capacitor RMS current (Icin(RMS)) varies with duty cycle (D), where N is the transformer turns ratio. The lowest input capacitor RMS current occurs at 50% duty cycle, while the highest occurs at 25% and 75%. Similarly, the ratio of the output capacitor ripple current (ΔIcout) to the inductor current change (ΔIL) depends on the duty cycle. Maximum ripple cancellation occurs at 50% duty cycle.
To maximize the reduction in filter capacitor current during an interleaved forward design, the duty cycle must be carefully selected. This can be achieved by adjusting the transformer turns ratio (N) based on the specific input and output voltage requirements. The equation below can be used to estimate N, where Vin(min) is the minimum input voltage, Dmax is the selected maximum duty cycle, and Vd represents the forward voltage drop of the output diode.
Once the maximum duty cycle and transformer turns ratio are determined, the minimum duty cycle (Dmin) can be calculated. Using the information from Figures 5 and 6, the worst-case filter capacitor current for the design can be derived.
A design example using the UCC28221 interleaved PWM controller demonstrates how the capacitor ripple current changes with duty cycle. A 200W converter was designed for an input voltage range of 36V to 76V with a 12V regulated output. A 2:1 input voltage change corresponds to a duty cycle of about 2:1. To optimize transformer reset and reduce capacitor current, a maximum duty cycle of 0.6 was chosen. Each converter operated at 500 kHz, and a Schottky diode with a Vd of 0.3V was used. This resulted in a transformer turns ratio of 1.75:1 and a minimum duty cycle of 0.28.
To suppress the peak input current, the output inductor was designed for 60% ripple current, resulting in a filter inductor of approximately 3.5µH. The output capacitor ripple specification was set to 200mV. At the minimum duty cycle of 0.28, the output capacitor ripple current was maximized, reaching around 3A. This required an ESR of less than 66mΩ to meet the output voltage requirements. Compared to a standard forward converter, the interleaved design allowed for a higher allowable ESR, improving flexibility in component selection.
The input capacitor RMS current was maximal at a duty cycle of approximately 28%, reaching around 2.4A. A conventional forward converter with a similar power stage had an input capacitor RMS current of about 4.7A. Thus, the interleaved converter reduced the input capacitor RMS current by approximately 50%.
Oscilloscope waveforms showed how the ripple current cancellation varied with duty cycle. At 50% duty cycle, the sum of the inductor currents was nearly DC, resulting in minimal output capacitor ripple current. At the maximum line voltage of 76V, the duty cycle was around 28%, and the peak-to-peak capacitor ripple current was approximately 60% of the inductor ripple current.
In conclusion, dual interleaved forward converters are beneficial for high-current and high-power density designs. They are ideal for intermediate bus converters and commercial power supply applications due to their ability to reduce input and output capacitor ripple currents. The inductor ripple current cancellation allows for a higher ESR in the output capacitor, reducing overall capacitance requirements and improving system efficiency.
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