Voltage regulator modules (VRMs) used to power modern computer central processing units (CPUs) have traditionally relied on multiphase interleaved buck converters. These VRMs are designed to meet the stringent regulation and transient response requirements of high-performance CPUs like the Pentium 4 and Athlon. Interleaved buck converters are well-suited for low-voltage, high-current applications because they reduce both the input capacitor RMS current and the output capacitor ripple current compared to standard buck converters. This results in a smaller output capacitor bank. By interleaving two forward converters, designers can also benefit from similar advantages as with interleaved buck converters. In high-current applications such as intermediate bus or commercial power supplies, an interleaved forward converter may offer greater benefits than a standard forward topology.
In traditional forward converters, the input current is discontinuous and must be filtered through the input capacitor (Cin), resulting in a higher RMS current (Icin). The output filter inductor (L1) typically has a ripple current (ΔIL1) of about 25% to 30% of the output current (Iout) to meet the output ripple voltage requirement (Vripple). The size of the output capacitor (Cout) depends on its ability to suppress this inductor ripple current. A formula can be used to estimate the maximum equivalent series resistance (ESR) and minimum output capacitance required. Usually, the ESR requirement dominates the selection of the capacitor, which necessitates a larger capacitance to handle the inductor ripple.
Interleaved dual forward converters operate with two forward converters operating 180 degrees out of phase. This configuration reduces both the input capacitor RMS current and the output capacitor ripple current. Each converter's input current is intermittent, but when interleaved, their combined input current becomes more continuous, resembling DC. As a result, the input capacitor only needs to filter the AC component, allowing it to be significantly smaller. The output current is the sum of the two inductor currents minus the capacitor current. Due to the 180-degree phase difference, the inductor ripple currents cancel each other, leading to a smoother output current and reduced ripple that the output capacitor must handle. This allows for a higher ESR in the output capacitor.
Theoretically, the ripple current cancellation feature could allow for a smaller filter inductor. However, in high-current applications, inductors are often kept at the same size to minimize total losses. The optimal reduction in capacitor ripple current occurs at a 50% duty cycle. At this point, the input capacitor RMS current is minimized, while it increases at duty cycles of 25% and 75%. The equations provided show how the input and output capacitor RMS currents vary with duty cycle. Similarly, the output capacitor ripple current is maximized when the duty cycle is not 50%, causing increased ripple that the capacitor must reject.
To achieve the best performance in an interleaved forward design, the duty cycle should be carefully selected. Adjusting the transformer turns ratio (N) based on input and output voltage requirements helps optimize the design. The following equation can estimate N: N = (Vin(min) × Dmax) / (Vout + Vd), where Vin(min) is the minimum input voltage, Dmax is the maximum duty cycle, and Vd is the forward voltage drop of the output diode. Once N and Dmax are determined, the minimum duty cycle (Dmin) can be calculated using the given formulas.
A design example involves a 200W interleaved forward converter using the UCC28221 PWM controller. Designed for an input range of 36V to 76V with a 12V output, the converter uses a 500kHz switching frequency and a Schottky diode with a Vd of 0.3V. With a maximum duty cycle of 0.6, the transformer turns ratio is set to 1.75:1, and the minimum duty cycle is 0.28. The output inductor is sized for 60% ripple current, resulting in an inductance of approximately 3.5μH.
The output capacitor must handle a ripple of up to 200mV. At the minimum duty cycle, the output capacitor ripple current reaches a peak of about 3A. This requires an ESR below 66mΩ. Compared to a standard forward converter, the interleaved version allows for a 1.7x higher ESR, offering more flexibility in capacitor selection. The input capacitor RMS current is reduced by about 50% compared to a conventional design, making the overall system more compact and efficient.
Oscilloscope waveforms illustrate the ripple current cancellation effect at different duty cycles. At 50%, the output inductor currents cancel almost completely, resulting in near-zero capacitor ripple. At lower duty cycles, such as 28%, the ripple current increases, but the interleaved design still offers significant improvements over the standard topology. Overall, interleaved forward converters are ideal for high-current, high-power-density applications, especially in intermediate bus and commercial power supplies, where reducing capacitor size and improving ESR tolerance are key design goals.
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