Abstract : EtherCAT is one of the fieldbuses widely used in the industrial control field. The EtherCAT Slave Controller is the key to realize the EtherCAT protocol data communication from the slave module. The self-controllable slave control chip is the industrial control system. An important basis for localized research and development. Based on the EtherCAT communication protocol and basic communication function logic, the FPGA state machine of EBUS encoding/decoding, Auto-forwarder and Loop-back funcTIon key communication nodes is designed. By analyzing the data state changes of each stage, the communication data of each node is verified. Sex. The experimental results show that the FPGA based on the above state machine realizes the basic communication link of EtherCAT slave station is completely feasible.
0 PrefaceEtherCAT is one of the fieldbuses widely used in industrial control by BECKHOFF. The bus has a full-duplex mode of operation and can transfer data based on the mode of master and slave connections. Low latency and high security. The EtherCAT Slave Controller (ESC) is the key to implementing the EtherCAT communication protocol from the slave module. At present, the communication functions based on the EtherCAT protocol are basically implemented by the slave chips such as ET1100/ET1200 [1-4]. However, due to the basic communication functions, such chips also have a large number of other functions, and such additional communication mechanisms are not disclosed to Chinese technicians, resulting in the inability to achieve full autonomy and control of such communication chips, and the adoption of effective security mechanisms. It is impossible to improve the security of the system. With the increasingly prominent information security issues in the field of industrial control, the application of such non-autonomous controllable communication chips introduces certain security risks to the operation of China's core control systems. In order to realize the complete autonomous control of the communication chip for the control system, it is necessary to realize the independent development of the EtherCAT communication protocol based on FPGA, and it is also an important premise to adopt the autonomous security mechanism to improve the security capability of the communication system.
The basic communication link is the core for transmitting and receiving EtherCAT protocol data. Therefore, based on the characteristics of EtherCAT protocol and data transmission mechanism, this study designs the FPGA state machine of key communication nodes to verify the feasibility of FPGA to realize the basic communication link function of EtherCAT slave controller. Sexuality lays an important foundation for improving EtherCAT's other communication functions and security mechanisms.
1 EtherCAT slave controller frameworkThe communication link between the EtherCAT master station and each slave station is shown in Figure 1. During the communication process, the data frame traverses all the slave devices. When the data frame passes through a certain slave station, the slave device analyzes the localized message according to the message command and reads/writes the data to the specified position. The data frame arrives at the end. After a slave, the slave sends the processed data frame to the primary station. After receiving the uplink telegram, the primary station processes the returned data, and the communication ends [5-6].
The EtherCAT slave controller mainly includes a data frame processing unit, an EBUS interface encoding/decoding module, an Auto-forwarder module, and a Loop-back funcTIon module. Taking the ET1100/ET1200 slave controller as an example, its internal frame is shown in Figure 2. It mainly includes MII, EBUS interface, EtherCAT data frame processing unit, Fieldbus memory management unit (FMMU, Fliedbus Memory Management Unit), and storage synchronization management. Channel (SM, SyncManager), distributed clock, PDI interface, ESC address space (including register and user data memory), EEPROM control, and status control, interrupt, watchdog and physical layer management.
Among them, the EtherCAT Processing Unit analyzes and processes the EtherCAT data stream. The Fieldbus Memory Management Unit (FMMU) is one of the core modules in the EtherCAT Slave Control IP Core and is used to implement logical addressing of the slave to the slave. The storage synchronization management channel (SM, SyncManager) implements data exchange between the primary station and the local application. Both the Ethercat frame and the PDI interface must poll the processor to determine if the other end has completed access. The PDI interface module is the application data interface of the ESC chip.
In the process of implementing the EtherCAT slave controller in the FPGA, if the data link path can be realized, the data frame can be transmitted to the FPGA through the EBUS and MII interfaces, and the FPGA identifies the data frame and performs CRC check to unpack the EtherCAT. The frame format and protocol commands are sent and the data frame is sent through the port connection status. Then, it can be stated that the EtherCAT slave controller can be developed independently in the FPGA. In the above data link, the EBUS interface involves the EBUS module. The EBUS module mainly parses the EBUS protocol and receives or transmits data through Manchester encoding/decoding. The FPGA identifies the data frame and performs CRC check on the Auto-Forwarder module. Send data frames through the Loop-back funcTIon module. The implementation process of each of the above modules is described below.
2 module implementation logic2.1 EBUS encoding / decoding module
For the EBUS implementation, the LVDS signal data rate of the EBUS interface is 100 Mb/s, and the EBUS interface is implemented by LVDS using Manchester encoded/decoded (Manchester encoded).
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