How can we effectively consolidate integration and reuse coverage while developing IP? Some functions and performance features of an IP can be configured. It is crucial to assess whether the IP can be normalized after various reasonable configurations. The first step in this process is to organize functional coverage into a hierarchical abstract model known as a cover model. This model helps in capturing the essential functionality of the IP across different configurations.
This paper discusses the importance of considering reuse coverage during IP development. In the context of hardware design IP, the focus is often on either implementing or integrating IP. Today, the development of IP is increasingly concentrated within large companies that have the expertise to ensure that configurable IP meets diverse user needs. Additionally, their deep customer base allows them to justify high R&D costs and produce silicon-proven IP that supports strong business growth. As a result, many companies rely on commercial IP for critical components. From the perspective of a verifier, there are often more opportunities to work with SoC companies to validate custom modules, core knowledge blocks, or IP units. At least one-third of SoC verification work involves testing IP modules. Therefore, SoC verifiers typically approach IP from the angle of integrated verification.
The perspective of this paper comes from the IP development side. Using this opportunity, I will walk through both the design and verification processes of IP development. Since the article uses PCIe as an example, my subsequent explanation of the IP development and integration verification process will also be based on PCIe.
For a mature PCIe IP, a commercial IP provider may sell its design IP, verification IP, or both. For instance, Synopsys offers both design and verification IP, meaning they provide not only a design solution but also recommend a corresponding verification solution. Whether you're designing or verifying, the first step is to define a PCIe functional configuration. This configuration is based on the SoC architecture, where appropriate functions, performance, and power parameters are selected. Both designers and verifiers use this configuration file to generate a customized design or verification IP. Then, the paired design and verification IPs can be set up in a test environment to perform IP-level or SoC-level verification. However, how do we quantify verification at both the IP and SoC levels? Functional coverage plays a key role here, but it’s often not generated alongside the IP itself. Why? Because highly configurable IPs make it challenging to define a universal functional coverage model. This paper illustrates the difficulty of defining functional coverage for configurable IPs using PCIe as an example.
Since some functions and performance aspects of IP are configurable—such as static disabling of certain features or dynamic control via emulators—these variations create challenges in defining a unified functional coverage model. The paper highlights that PCIe IP developers face more complex verification tasks than SoC verifiers, as they must account for all possible configurations, whereas SoC verifiers typically work with a limited set of configurations. Thus, the former focuses on ensuring the IP operates correctly under any reasonable configuration, while the latter checks if the IP integrates well into the system.
A major challenge in IP integration is that IP providers often lack visibility into how customers integrate their IP, and users may not fully understand the test coverage at the IP or SoC level. This gap arises because there's no clear data indicating the completeness of testing. If an IP provider can generate custom feature coverage along with the IP, it would greatly assist both the developer in verifying the IP and the integrator in validating its integration. This brings us to the question: can functional coverage be customized along with the IP profile? The paper presents a solution by demonstrating how configurable feature coverage is linked to each configured IP. Developers can then use these coverage metrics to determine if the verification of different IP configurations is complete.
If such functional coverage is provided to SoC integrators alongside the IP, it could enable better integration between IP and SoC-level verification. This would allow feedback to be collected on the functional coverage model, making it easier for both providers and integrators to review and improve the functional testing and integration of IP together.
The following is a summary of how this paper implements custom coverage for highly configurable IP.
The functional coverage is initially structured into a hierarchical abstract model called a cover model. This model consists of multiple block models, each representing key functions. These block models are combined to form the overall functional coverage, creating a comprehensive view of the IP's behavior.
Each block model has a tree-like structure, with the end nodes representing overlay variables or cover variables. These variables are abstract and describe the scope of the functions being tested rather than specific signals.
Cover variables can be grouped or cross-generated into cover groups. These cover groups are then mapped into an Excel spreadsheet, which also includes configuration variables. Configuration variables are important because they influence the range of values for certain cover variables or determine the presence of specific variables.
A Perl script reads the Excel spreadsheet and generates a hierarchical SystemVerilog covergroup. These covergroups are associated with block models that correspond to individual functions, forming a hierarchical structure. This ultimately results in a customized cover model tailored to the IP's configuration.
This approach aligns with some of the methods I currently use for defining functional coverage at the SoC level. First, functional coverage must be defined in an abstract way before it's implemented. Different functions can be treated as independent block models, and complex functions can be further broken down into child block models. The smallest units, which cannot be divided further, become cover variables. Some companies may prefer to define test points in plain text, leading to tiled SV covergroup definitions. However, using an Excel table ensures consistency and allows for script-based processing, enabling the decomposition of the design into functions and the hierarchical definition of block models at lower levels.
Compared to a tiled coverage model, a tree-like structure offers several advantages, particularly in terms of review and coverage analysis. For IP verification, the tree structure facilitates the hierarchical delivery of variables and targeted script processing. From a reuse perspective, if the process of converting Excel to SV covergroups is automated, the tree structure also makes future maintenance easier. For example, deleting a node from the tree (e.g., removing a function) would automatically remove all its sub-nodes. Similarly, grafting the IP-level coverage tree into the SoC-level coverage structure is a feasible method.
Conclusion
Automating the conversion from Excel to SV covergroups is a promising direction. However, it requires careful abstraction of functional test points into covergroups. For example, some functional tests may involve relationships that need to be further refined. This paper demonstrates a practical approach by combining scripts with Excel-based IP configuration variables to generate a hierarchical functional coverage model. This kind of coverage, if extended from the IP level to the SoC level, could serve as a more effective measure for IP integration testing.
Outdoor Cabinet Lock,Cabinet Material,Outdoor Telecom,Electrical Cabinet
Guangdong Yuqiu Intelligent Technology Co.,Ltd , https://www.cntcetltd.com