How can we effectively consolidate integration and reuse coverage while developing IP? Some functions and performance parameters of IP can be configured. It's essential to evaluate whether the IP can be standardized after various reasonable configurations. To address this, functional coverage is first organized into a hierarchical abstract model known as a "cover model." This approach helps in systematically capturing the key functionalities that need to be verified across different configurations.
This paper discusses how to consider reuse coverage during the development of IP. In the context of hardware design IP, the focus is often on either implementing or integrating IP. Currently, the development of IP is increasingly concentrated within large companies. These firms have more experience in ensuring that configurable IPs meet a wide range of user needs. Additionally, their strong customer base allows them to justify the high costs of R&D and silicon-proven IP, which leads to better business outcomes. Most companies today rely on commercial IP for critical components, driven by several factors. As a verifier, there may be more opportunities to work with SoC companies, performing validation on custom modules, core knowledge blocks, or IP units. At least one-third of SoC work involves verifying IP modules. Therefore, SoC verifiers typically look at IP from an integration perspective.
The perspective of this excerpt comes from the IP development side. Taking this opportunity, I can outline the IP development process from both design and verification viewpoints. Since the article uses PCIe as an example, my subsequent explanation of the IP development and integration verification process will also be based on PCIe.
[Image: How to consider reuse coverage when IP development]
For a mature PCIe IP, a commercial IP company might offer its design IP, verification IP, or both. For instance, Synopsys provides both design and verification IP, meaning they sell a complete solution and recommend purchasing their verification tools. Whether designing or verifying, the first step is to define a PCIe functional configuration. This configuration is based on the SoC architecture, where appropriate functions, performance, and power parameters are selected. Both designers and verifiers use this configuration file to generate customized IP. Then, the paired design and verification IPs can be set up in a test environment to perform IP-level or SoC-level verification. However, during verification, how do we quantify the verification effort at both IP and SoC levels? Functional coverage plays a crucial role here. But often, functional coverage isn't generated alongside the design or verification IP. Why? It’s because of the highly configurable nature of IP. This paper illustrates the challenges of defining functional coverage for such IP, using PCIe as an example.
Since some functions and performance parameters of IP are configurable—some may be disabled statically, while others may be dynamically controlled through configuration—the variations pose significant challenges in creating a unified functional coverage model. The developers of PCIe IP face more complex verification challenges than SoC verifiers, who only need to validate a limited set of configurations. The former must ensure that the IP functions correctly under all reasonable configurations, while the latter focuses on how well the IP integrates into the system.
A major challenge in IP integration is that IP providers don’t always know if the IP was properly integrated by different customers. Similarly, IP users may not fully understand the test coverage at the IP or SoC level. This gap arises due to the lack of clear data indicating the completeness of testing. If an IP provider can generate custom feature coverage along with the IP, it would provide valuable guidance for both internal verification and integration testing.
Is there a way to customize functional coverage based on the IP profile? This paper offers a solution. According to the conclusion, configurable feature coverage is tied to each specific IP configuration. When testing multiple configurations, developers can use these coverage metrics to assess the completeness of verification. If this functional coverage is provided alongside the IP, it can be used for both IP and SoC-level verification, allowing feedback to refine the coverage model. If both providers and integrators use the same model, it becomes easier to jointly review and improve the verification process.
**Here is a brief series outlining how this paper implements custom coverage for highly configurable IP.**
Functional coverage is first organized into a hierarchical abstract model called a "cover model."
This abstract model consists of multiple block models. Each block represents key functions that, when combined, form the overall functional coverage.
Each tree structure within the block model contains overlay variables, also known as cover variables. These variables are not tied to specific signals but instead describe the function ranges and relationships being tested.
Using these cover variables, you can create new groups, known as cover groups.
These cover variables and cover groups are stored in an Excel spreadsheet, along with configuration variables. Configuration variables are important because they determine the value ranges of certain cover variables or whether specific variables exist.
A Perl script reads the hierarchical Excel spreadsheet and generates a SystemVerilog covergroup. These covergroups are linked to block models, forming a hierarchical relationship and ultimately producing a customized cover model.
This method aligns with some of the approaches I currently use for defining functional coverage at the SoC level. First, functional coverage requires an abstract definition before implementation. Different functions can be represented as independent block models. Complex functions can be further broken down into child block models, with the smallest units becoming cover variables. Some companies may prefer to define test points in plain text, which can then be converted into tiled SV covergroups. By defining function points, you can extract them from an Excel table. With proper scripting, you can split the design into functions and use a hierarchical approach to define sub-block models.
What are the advantages of a tree-like coverage model compared to a tiled one? It makes review and analysis easier. For IP verification, the tree structure also facilitates the hierarchical delivery of variables and targeted script processing. From a reuse standpoint, if the process of converting Excel to SV covergroups is automated, the tree structure also benefits future maintenance, such as removing a node and its children, or grafting the IP-level coverage tree into the SoC-level structure.
**Conclusion:**
Automating the conversion from Excel to SV covergroups is a promising direction, but it requires careful abstraction of each functional point into a covergroup. For example, some functional tests may involve complex relationships, and some may be too abstract, requiring further subdivision. This paper presents a good attempt by combining scripts with Excel-based IP configuration variables to generate a hierarchical functional coverage model. If this coverage can be extended from the IP level to the SoC level, it could serve as a more effective measure of IP integration testing.
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