Elpida's vertical transistor structure DDR3 chip trial production successful

In a joint statement released today, Elpida Japan and Taiwan's Ruijing Semiconductor Co., Ltd. said that the two companies have successfully completed trial production of 1Gbit-density DDR3 DRAM chips in the 4F2 architecture. The trial production was led by Ruijing's R&D center. Ruijing's R&D center has been officially operating since last year, and they have been working with Elpida to develop 4F2 DRAM chip products. The two companies have now successfully created a 4F2 1Gbit density DDR3 DRAM chip based on 65nm design guidelines.

This 4F2 memory chip developed by Elpida and Ruijing was built using a vertical transistor architecture. The bitline and wordline of the memory chip were molded in silicon. The transistor cell area can be controlled at 2FX2F (F is the smallest pattern size in the transistor). Comparing the memory transistors designed with the 6F2 architecture, the area of ​​the 4F2 architecture transistor unit can be reduced by 30%, and the chip output can reach the level of the Elpida 50nm process product. In addition, the chip has excellent data retention characteristics and the vertical transistor structure used will also be necessary for the next generation of DRAM chips. At the same time, the 4F2 architecture can also meet the needs of DRAM for low-power mobile devices. (For more explanation on the 4F2/6F2 architecture, readers can refer to our previous article)

Elpida CEO Yukio Sakamoto said: "This successful trial production of 4F2 memory chips, we use the basic technology will be the development of the next generation of 20nm and higher specification memory chips essential technology. Elpida and Swiss Crystal's cooperation is the primary factor in our success. Now we are at the forefront of the memory chip industry."

The development of the 4F2 architecture memory chip was developed in close cooperation with Japanese and Taiwanese engineers from Elpida and Ruijing respectively.