Abstract: This paper introduces a communication bus RS485 master-slave communication method, which improves the RS485 bus collection speed. This method solves the shortcomings of slow master-slave communication, improves the communication speed, and is stable and reliable.
Keywords: RS485; master-slave call communication; ADM2483; ARM
Introduction: The industrial site often needs to collect multi-point data, analog signals or switching signals. This kind of situation generally uses the RS485 bus and uses a main band and multi-slave communication mode. In this mode, only two shielded cables are needed to facilitate the connection. The distance can be up to 1500m. The repeater can also increase the communication distance. The use of differential signals is good for electromagnetic interference. However, the communication speed of this mode cannot be too fast. Generally, the data of each subunit is collected in a master-slave mode. That is, the master unit summons the subunits in turn and summons the unit to that unit to upload data. The bus usage rights are completely allocated by the master unit. Each subunit cannot occupy the bus without authorization. If the number of units in the system is large, the time for which the main unit cyclically collects for a week is very long, and when the information of the subunit changes, it cannot be sent to the main unit in time, resulting in a slow response of the system to the mutation event. This article through the bus status check, from the initiative to solve the problem. ![]()
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General RS485 bus master-slave mode interface diagram
Bus detection RS485 bus interface diagram
hardware design
The entire system consists of a main unit and multiple subunits. The main unit consists of: ARM7 microcontroller, program memory, data memory, communication with subunits RS485, RS485 communication with the main unit, system power supply and communication isolation power supply; subunits include: MSP430 SCM, RS485 communication with subunits, system power supply and communication isolation power supply.
Overall system diagram
Main cell board design
ARM microcontroller is the core of the main unit, using Samsung's 32-bit ARM7TDMI core chip S3C44B0, the chip's maximum processing speed can reach 76MHZ, the bus is open, can expand the program memory FLASH and data memory SDRAM, the system expands the production of SST company The 39VF1601 and modern production HY57V641620HG, 2 UART serial interfaces, use ADI's isolated RS485 chip ADM2483 for interface level conversion, bus status detection using 74HC125 three-state gate chip.
Sub-cell board design
The subunit's microcontroller uses TI's MSP430F133 microcontroller, which handles up to 8 MHz, 8 Kbytes of on-chip FLASH memory, and 256 Kbytes of on-chip SRAM.
Power circuit
The power supply circuit uses a switching power supply. The input voltage range of the switching power supply is relatively wide, and the output DC voltage is 5V. The 3.3V power is output through the SP1117-3.3 and SP1117-2.5 chips. The isolated 5V power required by RS485 is obtained through the DC-DC module.
Bus detection circuit
The bus state detection uses 74HC125 three-state gate chip and two I/Os of the one-chip computer. When the system does not use the bus, the 74HC125 of each unit outputs a high-impedance state, and the bus is at a low level when a unit is to be used. When the bus, he first detects the bus state, if the bus is low, the unit quickly to 74HC125 output state, then the bus goes high, the unit occupied the bus, send data to the bus, send data to complete Change the 74HC125 to a high-impedance state. If it is detected that the bus is high, it waits for detection until the bus becomes occupied.
Isolated 485 circuit
Using ADI's ADM2483 chip for interface level conversion, the chip is isolated 485, dual power supply input and output isolation.
software design
Host program
The host program part needs to realize the receiving, processing and uploading of the data uploaded by each slave. The host receives subunit information through an RS485 serial port. The data format is hexadecimal, the data bit is 8 bits, a start bit, a stop bit, no parity bit, and the baud rate is 9600 bps. Serial port interrupts are used to receive signals. After the host program completes initialization, it waits for the slaves to send messages. When the host receives the first byte, it determines whether the byte is the device number. If it is not the device number, the number of received data is cleared. Zero, if it is the device number continues to receive the second byte; determine whether the second byte is the correct function, if the function is wrong, the number of received is cleared, and the function code is correct; the third byte is received. The byte is the number of bytes of information sent from the unit x, the total number of bytes sent from the unit is calculated as M = X + 3 + 2, 3 start bytes and 2 CRC checksums, the host receives After M bytes, it is first judged whether the CRC check code is correct. The error discards all information. If it is correct, the information of the slave unit is saved to the data area. At the end of this time, the host continues to wait for receiving.
Information is uploaded via an RS232 serial port. When the host receives the slave information, it processes the data and finds that the slave information has changed. The master is ready to send the slave information to the host computer, first re-initialize the send buffer, and then send the information to the host computer in turn through interrupts. The sending information includes the device number, function code, number of bytes sent, information bytes, and CRC checksum.
Communication Protocol: (in hexadecimal format)
Device No
function code
Send bytes N
Send N bytes
CRC check
The host unit receives the data flow diagram:
Conclusion
The technique mentioned in this article I have designed a system for verification. The system implements multipoint monitoring of switching signals, a master unit, 32 slave units, and each slave unit monitors 32 switches. 1024 switches can be monitored. Use a baud rate of 9600 bps. In the method of master-slave recall, the reaction time of switching signal monitoring is generally 20-30s. Using this type of bus detection method, the response speed of the switching signal is the slowest and does not exceed 1s, while the fast signal is only a few hundred ms. Improve the reaction time, and because there is no need to call from time to time, there is less bus data flow, which improves the stability of the bus.
references:
1. Li Zhaoqing’s PC and SCM Data Communication Technology Beijing University of Aeronautics and Astronautics Press
2. Tian Ze with Embedded System Development and Application Beijing University of Aeronautics and Astronautics Press
3, Hu Dazhao MSP430 series FLASH ultra-low power 16-bit microcontroller Beijing University of Aeronautics and Astronautics Press